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Ordering number : EN*5402
CMOS LSI
LC82103
Image-Processing LSI for Facsimile, Copier, and OCR Applications
Preliminaly Overview
The LC82103 converts the analog video signal from the CCD contact image sensor into high-precision binary image data. The LC82103 includes an 8-bit A/D converter and two 6-bit D/A converters. The 6-bit D/A converters are used for setting reference potential (high and low) of the 8-bit A/D converter. The LC82103 converts the input analog data to high precision multilevel data, that is produced by all pixel shading correction process, multilevel image resolution converting process, and correction process of user defined curves. That multilevel data is converted to high-precision bi-level image that is produced by using two dimensional filtering, a image separation method, and an error diffusion technique. Finally the LC82103 is able to reduce the image in the horizontal and vertical directions, too. The LC82103 requires absolutely no external memory since it limits the number of pixels processed to 3072/line. This LSI can implement the image processing used by FAX, copier, and OCR applications. * Binary image reduction (horizontal: thinning, fine black line retaining, fine white line retaining, vertical: thinning, fine black line retaining) * Single-voltage 5 V supply and low power due to CMOS process fabrication
Package Dimensions
unit: mm 3159-QFP64E
[LC82103]
Features
* Number of pixels processed: 3072 pixels/line * Processing speed: 250 ns/pixel maximum (When CLKIN = 32 MHz) * Built-in 8-bit A/D converter (with a sensor signal timing adjustment function) * Built-in two 6-bit D/A converters for setting the A/D converter high and low reference potential * Sensor drive circuit (supports CCDs and several CIS types) * Digital clamping (single-point clamping, even/odd clamping) * Distortion correction (white correction: all pixels, black correction: settable black correction subtracted data) * correction (support user-defined curves: 8-bit data) * Image area separation (characters, photographs, screened halftone areas) * Simple binary coding process (fixed threshold, brightness adaptive threshold) * Intermediate processing error diffusion (64 levels) * Multilevel image resolution conversion (1/2, 2/3, 3/2, 2/1)
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT) No. 5402-1/5
LC82103
Specifications
Absolute Maximum Ratings at Ta = 25C, GND = 0 V
Parameter Maximum supply voltage Maximum input and output voltages Allowable power dissipation Operating temperature Storage temperature Soldering temperature endurance Symbol VDD max VI, VO max Pd max Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 350 -30 to +70 -55 to +125 350 235 Unit V V mW C C C C
Allowable Operating Ranges at Ta = -30 to +70C, GND = 0 V
Parameter Supply voltage Input voltage Symbol VDD VIN Conditions Ratings min 4.5 0 typ max 5.5 VDD Unit V V
DC Characteristics at Ta = -30 to +70C, GND = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input leakage current Output high-level voltage Output low-level voltage Output leakage current Current drain Symbol VIH VIL IIH, L VOH VOL IOZ IDD VIN = VDD, VSS IOH = -3 mA IOL = 3 mA At high impedance CLKIN = 32 MHz -10 40 -10 2.4 0.4 +10 70 Conditions Ratings min 2.2 0.8 +10 typ max Unit V V A V V A mA
Analog Characteristics
Parameter [D/A Converter] Resolution Internal resistance [A/D Converter] When the ATAPL potential = 0.8 V, ATAPH potential = 4.2 V Resolution Linearity error Differential linearity error Internal resistance 330 8 1 1 bit LSB LSB 6 4.8 bit k Symbol Conditions min typ max Unit
No. 5402-2/5
LC82103 Block Diagram
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol D7 D6 D5 D4 D3 D2 D1 D0 DGND DVDD A8 A7 A6 A5 A4 A3 DGND A2 A1 A0 WR RD A12 DVDD CLKIN A11 A10 A9 I/O B B B B B B B B P P I I I I I I P I I I I I I P I I I I Digital system ground Digital system ground
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Function
CPU interface data bus D7 is the MSB, and D0 is the LSB.
Digital system power supply
CPU interface address bus A12 is the MSB, and A0 is the LSB.
CPU interface address bus
CPU interface write signal CPU interface read signal CPU interface address bus Digital system power supply System clock input
CPU interface address bus
Continued on next page. No. 5402-3/5
LC82103
Continued from preceding page.
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol CS ICLK TRIG RESET SAMP/LININT TEST REF AGND DALRL DAHRL AIN TEMP ATAPH DAHRH AVDD DALRH ATAPL AGND PD7/SD PD6/SDCK DGND PD5/SDE PD4/PP4 PD3/PP3 PD2/PP2 PD1/PP1 PD0/PP0 DVDD DACK/PP5 DREQ/PP6 MTP/PP7 CLK2 CLK1 RS SH DGND I/O I I I I O I I P I I I I O I P I O P O O P O B B B B B P B B B O O O O P Digital system ground Sensor drive signal outputs Digital system power supply DMA data acknowledge signal input/general-purpose I/O port DMA data request signal output/general-purpose I/O port Motor drive timing signal output/general-purpose I/O port DMA output/general-purpose I/O ports CPU interface chip select signal input External sampling point signal input External trigger signal input System reset A/D converter sampling point monitor signal output/LINE signal output Test pins (Must be connected to the digital system ground during normal operation.) DRAM refresh signal input Analog system ground D/A converter low reference input for A/D converter low reference D/A converter high reference input for A/D converter high reference Sensor signal input Temperature signal input Analog mid-level signal used as A/D converter high reference D/A converter high reference input for A/D converter high reference Analog system power supply D/A converter high reference input for A/D converter low reference Analog mid-level signal used as A/D converter low reference Analog system ground DMA output/serial data output DMA output/serial data transfer clock Digital system ground DMA output/serial data output valid period indicator Function
No. 5402-4/5
LC82103 Application Example
1. C1 is a 0.01 F laminated ceramic capacitor 2. The video signal from the image sensor must be set up with a polarity that has white data being the highest potential and black data being the lowest. If the peak level of the video signal from the image sensor does not reach a maximum value of 4.2 V, a level conversion circuit should be inserted to allow the full dynamic range of the A/D converter to be taken advantage of. 3. Although AGND and DGND are fully isolated within the LSI, AVDD and DVDD are connected through the LSI substrate. Accordingly, AVDD and DVDD must be set up so that there is no potential difference between them. Also, the time lag between these signals must be under 3 ms when power is first applied or when power is turned off.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5402-5/5

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